Power line communication (PLC) is a special communication mode in which voice or data is transmitted by using high-voltage power lines (typically referring to 35 kV or higher voltage levels in the field of power line communication), medium-voltage power lines (referring to 10 kV voltage level) or low-voltage power distribution lines (380/220V subscriber lines) as information transmission media. Its most outstanding characteristic is that a network is not required to be re-erected and the data can be transmitted as long as there are power lines.
HomePlug Powerline Alliance is a protocol applied to power line communication, mainly recommended by the standardization organization of power line communication technology. As one of its core technologies, 3072-point fast Fourier transform (FFT) is used in a modem defined by its physical layer to implement modulation functions of orthogonal frequency division multiplexing (OFDM).
At present, main methods in the industry for implementing the FFT include radix-2 and radix-4 algorithms, which have been developed into many mature methods from software emulation to hardware implementation. There are a variety of corresponding processors and field programmable gate array (FPGA) IP cores in engineering. However, these algorithms can only process Fourier transform of power of 2 or power of 4 points. For data of non-power of 2 or non-power of 4 points, the original data can be interpolated to be data of power of 2 or power of 4 points in an interpolation manner, and then the interpolated data are processed by using radix-2 or radix-4 fast Fourier transform. This, however, brings two major problems. 1) Errors are bound to be brought since interpolation is used. 2) Because of changes in a sampling rate, complexity of synchronization is added in OFDM systems. For the fast Fourier transform which does not satisfy the data of power of 2 or power of 4 as described above, if data points are complex numbers, mixed-radix FFT algorithms, including mainly Cooley-Tukey algorithm and Winograd Fourier transform algorithm (WFTA) and so on, are commonly used in the industry presently. However, such algorithms are often complicated to implement in hardware, and require more storage spaces to be opened for storage of intermediate operation results and changes of data positions, thereby increasing resources of random access memories (RAMs) and causing more serious problem of trace congestion in chips. In improvement of processing performance of fast Fourier transform, main means used presently are to increase operation parallelism and use a local asynchronous structure, i.e., increase a local processing dominant frequency. Increasing of operation parallelism is a relatively commonly-used means. While the local asynchronous will bring a greater challenge to both circuit design and low power consumption, thus such means will not be used for chips sensitive to cost and power consumption. However, increasing of algorithm parallelism will increase in turn complexity of storage of the intermediate operation results. To avoid performance loss resulting from occurrence of bubbles in the operation due to conflicts caused by accessing data in the operational process, a method in which operation of data and access of intermediate results are implemented in a ping-pong storage manner is proposed. Although this method decreases the complexity of access of the intermediate results, the consequence that more RAMs are used is also brought, areas and power consumptions of the chips are increased dramatically in fast Fourier transform operation of big points.